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| 74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs March 2001 Revised September 2001 74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The VCX32500 is an 36-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in a highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). The VCX32500 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V-3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (A to B, B to A) 2.9 ns max for 3.0V to 3.6V VCC 3.5 ns max for 2.3V to 2.7V VCC 7.0 ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Static Drive (IOH/IOL) 24 mA @ 3.0V VCC 18 mA @ 2.3V VCC 6 mA @ 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistors; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74VCX32500GX (Note 2) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] Note 2: BGA package available in Tape and Reel only. (c) 2001 Fairchild Semiconductor Corporation DS500403 www.fairchildsemi.com 74VCX32500 Connection Diagram FBGA Pin Assignments 1 A B C D E F G H J K L M N P R T U V 1A2 1A4 1A6 1A8 1A10 1A12 1A14 1A15 1A17 NC 2A2 2A4 2A6 2A8 2A10 2A12 2A14 2A15 2A17 2 1A1 1A3 1A5 1A7 1A9 1A11 1A13 1A16 1A18 2A1 2A3 2A5 2A7 2A9 2A11 2A13 2A16 2A18 3 4 5 1B1 1B3 1B5 1B7 1B9 1B11 1B13 1B16 1B18 CLKAB2 2B1 2B3 2B5 2B7 2B9 2B11 2B13 2B16 2B18 6 1B2 1B4 1B6 1B8 1B10 1B12 1B14 1B15 1B17 NC 2B2 2B4 2B6 2B8 2B10 2B12 2B14 2B15 2B17 LEAB1 CLKAB1 OEAB1 GND VCC GND GND VCC GND GND GND VCC GND GND VCC GND OEBA1 CLKBA1 GND GND GND VCC GND GND VCC GND OEAB2 GND VCC GND GND VCC GND LEAB2 LEBA1 OEBA2 CLKBA2 LEBA2 GND (Top Thru View) W Pin Descriptions Pin Names OEABn OEBAn Description Output Enable Input for A to B Direction (Active HIGH) Output Enable Input for B to A Direction (Active LOW) Function Table (Note 3) Inputs OEABn LEABn CLKABn L H H H H X H H L L L L X X X An X L H L H X X Outputs Bn Z L H L H B0 (Note 4) B0 (Note 5) LEABn, LEBAn Latch Enable Inputs CLKABn, CLKBAn 1A1-1A18 2A1-2A18 1B1-1B18 2B1-2B18 Clock Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs H L H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 3: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CLKBA. OEBA is active LOW. Note 4: Output level before the indicated steady-state input conditions were established. Note 5: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. www.fairchildsemi.com 2 74VCX32500 Logic Diagrams 3 www.fairchildsemi.com 74VCX32500 Absolute Maximum Ratings(Note 6) Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 7) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5 to VCC + 0.5V -50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C Recommended Operating Conditions (Note 8) Power Supply Operating Data Retention Only Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 6: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 7: IO Absolute Maximum Rating must be observed. Note 8: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. 1.65V to 3.6V 1.2V to 3.6V -0.3V to 3.6V 0V to VCC 0.0V to 3.6V 24 mA 18 mA 6 mA -40C to +85C DC Electrical Characteristics (2.7V < VCC 3.6V) Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 24 mA II IOZ IOFF ICC ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0V VI 3.6V 0V VO 3.6V VI = VIH or VIL 0V (VI, VO) 3.6V VI = VCC or GND VCC (VI, VO) 3.6V (Note 9) VIH = VCC - 0.6V Note 9: Outputs disabled or 3-STATE only. Conditions VCC (V) 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7 3.0 3.0 2.7-3.6 2.7-3.6 0 2.7-3.6 2.7-3.6 2.7-3.6 Min 2.0 Max Units V 0.8 VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5.0 10 10 40 40 750 V V V A A A A A www.fairchildsemi.com 4 74VCX32500 DC Electrical Characteristics (2.3V VCC 2.7V) Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -6 mA IOH = -12 mA IOH = -18 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 12 mA IOL = 18 mA II IOZ IOFF ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current 0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 10) Note 10: Outputs disabled or 3-STATE only. Conditions VCC (V) 2.3-2.7 2.3-2.7 2.3-2.7 2.3 2.3 2.3 2.3-2.7 2.3 2.3 2.3-2.7 2.3-2.7 0 2.3-2.7 2.3-2.7 Min 1.6 Max Units V 0.7 VCC - 0.2 2.0 1.8 1.7 0.2 0.4 0.6 5.0 10 10 40 40 V V V A A A A DC Electrical Characteristics (1.65V VCC < 2.3V) Symbol VIH VIL VOH VOL II IOZ IOFF ICC Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current IOH = -100 A IOH = -6 mA IOL = 100 A IOL = 6 mA 0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 11) Note 11: Outputs disabled or 3-STATE only. Conditions VCC (V) 1.65 - 2.3 1.65 - 2.3 1.65 - 2.3 1.65 1.65 - 2.3 1.65 1.65 - 2.3 1.65 - 2.3 0 1.65 - 2.3 1.65 - 2.3 Min 0.65 x VCC Max Units V 0.35 x VCC VCC - 0.2 1.25 0.2 0.3 5.0 10 10 40 40 V V V A A A A 5 www.fairchildsemi.com 74VCX32500 AC Electrical Characteristics (Note 12) TA = -40C to +85C, CL = 30 pF, RL = 500 Symbol fMAX tPHL tPLH tPHL tPLH tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW Setup Time Hold Time Pulse Width Output Disable Time Parameter Maximum Clock Frequency Propagation Delay Bus to Bus Propagation Delay Clock to Bus Propagation Delay LE to Bus Output Enable Time VCC = 3.3V 0.3V Min 250 0.6 0.6 0.6 0.6 0.6 1.5 1.0 1.5 2.9 4.2 3.8 3.8 3.7 Max VCC = 2.5 0.2V Min 200 0.8 0.8 0.8 0.8 0.8 1.5 1.0 1.5 3.5 5.3 4.9 4.9 4.2 Max VCC = 1.8 0.15V Min 100 1.5 1.5 1.5 1.5 1.5 2.5 1.0 4.0 7.0 9.8 9.8 9.8 7.6 Max MHz ns ns ns ns ns ns ns ns Units Note 12: For CL = 50pF, add approximately 300ps to the AC maximum specification. Dynamic Switching Characteristics Symbol VOLP Parameter Quiet Output Dynamic Peak VOL VOLV Quiet Output Dynamic Valley VOL VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 1.8 2.5 3.3 1.8 2.5 3.3 TA = +25C Typical 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 Units V V V Capacitance Symbol CIN CI/O CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VI = 0V or VCC VCC = 1.8V, 2.5V, or 3.3V, VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz VCC = 1.8V, 2.5V or 3.3V Conditions TA = +25C 6 7 20 Units pF pF pF www.fairchildsemi.com 6 74VCX32500 AC Loading and Waveforms FIGURE 1. AC Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open 6V at VCC = 3.3 0.3V; VCC x 2 at VCC = 2.5 0.2V; 1.8 0.15V GND FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.5V 0.2V VCC /2 VCC /2 VOL + 0.15V VOH - 0.15V 1.8 0.15V VCC /2 VCC /2 VOL + 0.15V VOH - 0.15V 7 www.fairchildsemi.com 74VCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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